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CY62256EV18 mobl ? 256-kbit (32 k 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-69650 rev. *b revised september 4, 2012 256-kbit (32 k 8) static ram features very high speed: 70 ns temperature ranges: ? industrial: ?40 c to +85 c wide voltage range: 1.65 v to 2.25 v pin compatible with cy62256n ultra low standby power ? typical standby current: 1 a ? maximum standby current: 4 a ultra low active power ? typical active current: 1.3 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power offered in pb-free 28-pin narrow soic package functional description the CY62256EV18 is a high performance cmos static ram module organized as 32 k words by 8-bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. placing the device in standby mode reduces power consumption by more than 99 percent when deselected (ce high). the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or a write operation is in progress (ce low and we low). to write to the device, take chip enable (ce ) low and write enable (we ) low. data on the eight i/o pins is then written into the location specified on the address pin (a 0 through a 14 ). to read from the device, take chip enable (ce low) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 column decoder row decoder sense amps inputbuffer power down we oe i/o 0 ce i/o 1 i/o 2 i/o 3 32k x 8 arra y i/o 7 i/o 6 i/o 5 i/o 4 a 10 a 13 a 11 a 12 a a 14 a 1 0 logic block diagram
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 2 of 14 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagrams .......................................................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc solutions ......................................................... 14
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 3 of 14 pin configuration figure 1. 28-pin narrow soic product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 (a) f = 1 mhz f = f max min typ [1] max typ [1] max typ [1] max typ [1] max CY62256EV18ll industrial 1.65 1.8 2.25 70 1.3 2.0 11 16 1 4 notes 1. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 4 of 14 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential .......................................................?0.2 v to 2.45 v dc voltage applied to outputs in high z state [2, 3] ......................................?0.2 v to 2.45 v dc input voltage [2, 3] ...................................?0.2 v to 2.45 v output current into outputs (low) ............................. 20 ma static discharge voltage (mil-std-883, method 3015) ................................ > 2001 v latch-up current .................................................... > 200 ma operating range device range ambient temperature v cc [4] CY62256EV18ll industrial ?40 c to +85 c 1.65 v to 2.25 v electrical characteristics over the operating range parameter description test conditions 70 ns unit min typ [5] max v oh output high voltage i oh = ?0.1 ma 1.4 ? ? v v ol output low voltage i ol = 0.1 ma ? ? 0.2 v v ih input high voltage v cc = 1.65 v to 2.25 v 1.4 ? v cc + 0.2 v v v il input low voltage v cc = 1.65 v to 2.25 v ?0.2 ? 0.4 v i ix input leakage current gnd < v i < v cc ?1 ? +1 a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 2.25 v i out = 0 ma cmos levels ?1116ma f = 1 mhz ? 1.3 2.0 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ??? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v f = f max (address and data only), f = 0 (oe and we ), v cc = 2.25 v ?14a i sb2 [6] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 2.25 v ?14a notes 2. v il(min) = ?2.0 v for pulse durations less than 20 ns. 3. v ih(max) = v cc + 0.5 v for pulse durations less than 20 ns. 4. full device ac operation assumes a 100 s ramp time from 0 to v cc(min) and 200 s wait time after v cc stabilization. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 6. chip enables (ce ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 5 of 14 capacitance parameter [7] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [7] description test conditions 28-pin soic unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 76.56 c/w ? jc thermal resistance (junction to case) 36.07 c/w ac test loads and waveforms figure 2. ac test loads and waveforms v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: thevenin equivalent all input pulses r th r1 parameters 1.8 v unit r1 13500 ? r2 10800 ? r th 6000 ? v th 0.8 v note 7. tested initially and after any design or process changes that may affect these parameters.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 6 of 14 data retention characteristics over the operating range parameter description conditions min typ [8] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [9] data retention current v cc = 1.0 v, ce > v cc ?? 0.2 v, v in > v cc ?? 0.2 v or v in < 0.2 v ??3a t cdr [10] chip deselect to data retention time 0??ns t r [11] operation recovery time 70 ? ? ns data retention waveform figure 3. data retention waveform [12] v cc(min) v cc(min) t cdr v dr > 1.0 v data retention mode t r v cc ce notes 8. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 9. chip enables (ce ) must be at cmos level to meet the i sb2 / i ccdr spec. other inputs can be left floating. 10. tested initially and after any design or proc ess changes that may affect these parameters. 11. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 s or stable at v cc(min) ? 100 s. 12. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 7 of 14 switching characteristics over the operating range parameter [13] description 70 ns unit min max read cycle t rc read cycle time 70 ? ns t aa address to data valid ? 70 ns t oha data hold from address change 5 ? ns t ace ce low to data valid ? 70 ns t doe oe low to data valid ? 35 ns t lzoe oe low to low z [14] 5?ns t hzoe oe high to high z [14, 15] ?25ns t lzce ce low to low z [14] 5 ? ns t hzce ce high to high z [14, 15] ?25ns t pu ce low to power-up 0 ? ns t pd ce high to power-down ? 70 ns write cycle [16] t wc write cycle time 70 ? ns t sce ce low to write end 60 ? ns t aw address setup to write end 60 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 50 ? ns t sd data setup to write end 30 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [14, 15] ?25ns t lzwe we high to low z [14] 5?ns notes 13. test conditions for all parameters other than tri-state paramete rs assume signal transition time of 3 ns or less (1 v/ns), t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 14. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 15. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing s hould be referenced to the edge of the signal that terminates the write.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 8 of 14 switching waveforms figure 4. read cycle no. 1 (address transition controlled) [17, 18] figure 5. read cycle no. 2 (oe controlled) [18, 19] figure 6. write cycle no. 1 (we controlled) [20, 21, 22] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high address ce data out v cc supply current oe data valid t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe address ce we data i/o oe note 23 notes 17. the device is continuously selected. oe , ce = v il . 18. we is high for read cycle. 19. address valid before or similar to ce transition low. 20. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hold timing should be referenced to the edge of the signal that t erminates the write. 21. data i/o is high impedance if oe = v ih . 22. if ce goes high simultaneously with we high, the output remains in high impedance state. 23. during this period, the i/os are in output state. do not apply input signals.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 9 of 14 figure 7. write cycle no. 2 (ce controlled) [24, 25, 26] figure 8. write cycle no. 3 (we controlled, oe low) [26] switching waveforms (continued) t wc data valid t aw t sa t pwe t ha t hd t sd t sce address ce data i/o we data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe address ce we data i/o note 27 notes 24. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input setup and hol d timing should be referenced to the edge of the signal that t erminates the write. 25. data i/o is high impedance if oe = v ih . 26. if ce goes high simultaneously with we high, the output remains in high impedance state. 27. during this period, the i/os are in output state. do not apply input signals.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 10 of 14 truth table ce we oe inputs/outputs mode power hx [28] x [28] high z deselect/power-down standby (i sb ) l h l data out read active (i cc ) llx [28] data in write active (i cc ) l h h high z selected, outputs disabled active (i cc ) note 28. the ?x? (don?t care) state for the ce / oe / we in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted.
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 11 of 14 ordering information speed (ns) ordering code package diagram package type operating range 70 CY62256EV18ll-70snxi 51-85092 28-pin (300 -mil) narrow soic (pb-free) industrial contact your local cypress sales repres entative for availability of these parts. ordering code definitions temperature grade: i = industrial = ?40 c to +85 c pb-free package type: sn = 28-pin narrow soic speed grade: 70 ns low power v18 = 1.8 v process technology: e = 90 nm density: 256 kbit mobl sram family company id: cy = cypress 256 e - 70 i sn ll cy 62 v18 x
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 12 of 14 package diagrams figure 9. 28-pin snc (300 mils) sn28.3 (narrow body) package outline, 51-85092 51-85092 *e
CY62256EV18 mobl ? document #: 001-69650 rev. *b page 13 of 14 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable sram static random access memory soic small outline integrated circuit we write enable symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere ns nanosecond ? ohm pf picofarad vvolt wwatt
document #: 001-69650 rev. *b revi sed september 4, 2012 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. CY62256EV18 mobl ? ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: CY62256EV18 mobl ? , 256-kbit (32 k 8) static ram document number: 001-69650 revision ecn submission date orig. of change description of change ** 3334904 09/07/2011 rame new data sheet *a 3413173 10/18/2011 rame changed stat us from preliminary to final. *b 3733339 09/04/2012 jish fixed typo errors. sunset review.

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